Information processing system

ABSTRACT

According to an embodiment, an information processing system solves a combinatorial optimization problem. The information processing system includes an Ising machine and a host unit. The Ising machine is hardware configured to perform a search process for searching for the ground state of an Ising model that represents the combinatorial optimization problem. The host unit is hardware connected to the Ising machine via an interface and configured to control the Ising machine. In the search process, for each of a plurality of Ising spins, the Ising machine alternately repeats an auxiliary variable update process for updating an auxiliary variable by a main variable and a main variable update process for updating the main variable by the auxiliary variable multiple times. Prior to the search process, the host unit transmits, to the Ising machine, an initial value of the auxiliary variable corresponding to each of the plurality of Ising spins.

CROSS-REFERENCE TO RELATED APPLICATIONS

This application is based upon and claims the benefit of priority fromJapanese Patent Application No. 2020-136775, filed on Aug. 13, 2020; theentire contents of which are incorporated herein by reference.

FIELD

Embodiments described herein relate generally to an informationprocessing system.

BACKGROUND

Optimization of complex systems in various application fields such asfinance, logistics, control, and chemistry often results in mathematicalcombinatorial optimization problems. The combinatorial optimizationproblem is the problem of finding a combination of discrete values thatminimizes a function of discrete variables, the function being called acost function.

In recent years, a specific purpose device that performs a searchprocess for the ground state of an Ising model has been attractingattention, the specific purpose device being called an Ising machine.The problem of searching for the ground state of the Ising model iscalled an Ising problem. The Ising problem is a combinatorialoptimization problem that minimizes a cost function given by a quadraticfunction of a variable representing a binary value (Ising spin). Thecost function is called Ising energy. Many practical combinatorialoptimization problems can be transformed into the Ising problems.Therefore, a system that solves the combinatorial optimization problemcan solve a target combinatorial optimization problem by using the Isingmachine.

The system that solves the combinatorial optimization problem includesthe Ising machine that performs a search process for the ground state ofthe Ising model and a host unit that performs a process other than asearch process. Further, the Ising problem is defined by a couplingcoefficient group (J matrix) and an external magnetic field coefficientgroup (h vector).

In such a system that solves the combinatorial optimization problem, thehost unit transmits the J matrix and the h vector to the Ising machine,and receives a value of each of a plurality of optimized Ising spinsfrom the Ising machine. In addition, the Ising machine receives the Jmatrix and the h vector from the host unit, and returns the value ofeach of the plurality of Ising spins optimized so as to minimize theIsing energy. It is required for such a system that solves thecombinatorial optimization problem to efficiently transmit and receiveinformation between the host unit and the Ising machine, and shorten thetime taken from the start of calculation of the combinatorialoptimization problem to the output of the solution.

BRIEF DESCRIPTION OF THE DRAWINGS

FIG. 1 is a diagram illustrating a functional configuration of aninformation processing system according to a first embodiment;

FIG. 2 is a diagram illustrating a graph representing an Ising model;

FIG. 3 is a diagram illustrating variables stored in an Ising machine;

FIG. 4 is a flowchart illustrating a flow of a search process performedby the Ising machine;

FIG. 5 is a diagram illustrating a hardware configuration of theinformation processing system;

FIG. 6 is a sequence diagram illustrating a process flow of theinformation processing system;

FIG. 7 is a diagram illustrating a hardware configuration of aninformation processing system according to a second embodiment;

FIG. 8 is a flowchart of a first example of the second embodiment;

FIG. 9 is a timing chart of the first example of the second embodiment;

FIG. 10 is a flowchart of a second example of the second embodiment;

FIG. 11 is a flowchart illustrating a flow of a preprocess;

FIG. 12 is a timing chart of the second example of the secondembodiment;

FIG. 13 is a diagram illustrating a functional configuration of aninformation processing system according to a third embodiment;

FIG. 14 is a flowchart of the third embodiment;

FIG. 15 is a flowchart of a timer interrupt of the third embodiment;

FIG. 16 is a timing chart of the third embodiment;

FIG. 17 is a flowchart of a timer interrupt of a fourth embodiment;

FIG. 18 is a timing chart of the fourth embodiment;

FIG. 19 is a diagram illustrating process times in a case of notperforming reconfiguration and in a case of performing reconfiguration;and

FIG. 20 is a diagram illustrating coupling information including acoupling coefficient.

DETAILED DESCRIPTION

According to an embodiment, an information processing system solves acombinatorial optimization problem. The information processing systemincludes an Ising machine and a host unit. The Ising machine is hardwareconfigured to perform a search process for searching for a ground stateof an Ising model that represents the combinatorial optimizationproblem. The host unit is hardware that is connected to the Isingmachine via an interface and is configured to control the Ising machine.In the search process, the Ising machine is configured to: store a mainvariable and an auxiliary variable that correspond to each of aplurality of Ising spins included in the Ising model in association witheach other; alternately repeat an auxiliary variable update process forupdating the auxiliary variable by the main variable and a main variableupdate process for updating the main variable by the auxiliary variablemultiple times for each of the plurality of Ising spins; and output, asa search result, a value based on the main variable corresponding toeach of the plurality of Ising spins after alternately repeating themain variable update process and the auxiliary variable update processmultiple times. The host unit is configured to: prior to the searchprocess, transmit, to the Ising machine, an initial value of theauxiliary variable corresponding to each of the plurality of Isingspins; and after the search process, receive the search result from theIsing machine and output a solution of the combinatorial optimizationproblem based on the received search result.

First Embodiment

FIG. 1 is a diagram illustrating a functional configuration of aninformation processing system 10 according to a first embodiment.

The information processing system 10 is a device that solves acombinatorial optimization problem. The information processing system 10according to the first embodiment includes an Ising machine 12 and ahost unit 14.

The Ising machine 12 is hardware that performs a search process forsearching for the ground state of an Ising model that represents thecombinatorial optimization problem. The Ising machine 12 is areconfigurable semiconductor device such as a field programmable gatearray (FPGA). Note that, in the first embodiment, the Ising machine 12does not have to be a reconfigurable semiconductor device. In the firstembodiment, the Ising machine 12 may be, for example, a semiconductordevice that is not reconfigurable or a processing circuit that performsinformation processing according to a program.

The host unit 14 is hardware that is connected to the Ising machine 12via a physical interface and controls the Ising machine 12. The hostunit 14 is a processing circuit that performs information processingaccording to a program. The host unit 14 performs a process other thanthe search process performed by the Ising machine 12 among a series ofprocesses for solving the combinatorial optimization problem.

When searching for the ground state of the Ising model that representsthe combinatorial optimization problem to be solved, the host unit 14transmits, to the Ising machine 12 via the interface, a J matrix and hvector, which are definition information that defines the Ising model, acontrol parameter for controlling the search process performed by theIsing machine 12, and an initial value of each of a plurality ofauxiliary variables (p₁, P₂, p₃, . . . ) (which will be described indetail later). Note that the host unit 14 may further transmit aninitial value of each of a plurality of main variables (x₁, x₂, x₃, . .. ) (which will be described in detail later) to the Ising machine 12via the interface.

The Ising machine 12 performs the search process for searching for theground state of the Ising model defined by the J matrix and the hvector. At the start of the search process, the Ising machine 12substitutes the initial value received from the host unit 14 in each ofthe plurality of auxiliary variables (p₁, P₂, p₃, . . . ). Further, atthe start of the search process, the Ising machine 12 substitutes, as aninitial value, a predetermined value such as 0 in each of the pluralityof main variables (x₁, x₂, x₃, . . . ). The Ising machine 12 maygenerate a value based on a random number or the like, and substitute,as an initial value, the generated value in each of the plurality ofmain variables (x₁, x₂, x₃, . . . ). Note that in a case where the Isingmachine 12 receives the initial value of each of the plurality of mainvariables (x₁, x₂, x₃, . . . ) from the host unit 14, the Ising machine12 substitutes the received value in each of the plurality of mainvariables (x₁, x₂, x₃, . . . ). Further, the Ising machine 12substitutes an initial value in each of the plurality of main variables(x₁, x₂, x₃, . . . ) and each of the plurality of auxiliary variables(p₁, p₂, p₃, . . . ), and then starts searching.

By performing the search process, the Ising machine 12 can calculate thevalues of the plurality of main variables (x₁, x₂, x₃, . . . ) thatminimize Ising energy in the Ising model. Further, the Ising machine 12transmits, as a search result, values of N Ising spins (s₁, s₂, s₃, . .. ) obtained by binarizing the respective values of the plurality ofmain variables (x₁, x₂, x₃, . . . ) after the search process, to thehost unit 14 via the interface. The Ising machine 12 may transmit, asthe search result, the values of the plurality of main variables (x₁,x₂, x₃, . . . ) after the search process, to the host unit 14. Then, thehost unit 14 outputs a value of each of a plurality of Ising spins (s₁,s₂, s₃, . . . ) as the solution of the combinatorial optimizationproblem.

FIG. 2 is a diagram illustrating a graph representing the Ising model.Energy E(s) of the Ising model including N Ising spins is expressed bythe following Equation (1).

$\begin{matrix}{{E(s)} = {{{- \frac{1}{2}}{\sum\limits_{i = 1}^{N}{\sum\limits_{j = 1}^{N}{J_{i,j}s_{i}s_{j}}}}} + {\sum\limits_{i = 1}^{N}{h_{i}s_{i}}}}} & (1)\end{matrix}$

N is the number of Ising spins included in the Ising model, and is aninteger of 3 or more. i and j represent indexes of the Ising spin andare integers greater than or equal to 1 and less than or equal to N.s_(i) represents the i-th Ising spin. s_(j) represents the j-th Isingspin. s_(i) and s_(j) represent either −1 or +1. Note that N Ising spinsmay be collectively referred to as an s vector (s₁, s₂, . . . , ands_(N)). The s vector represents the arrangement of −1 or +1 in N Isingspins.

J_(ij) is an element in a row i and a column j in the J matrix. The Jmatrix is a square matrix of N rows and N columns, in which symmetricelements are the same as each other (J_(ij)=J_(ji)). In the Ising model,a coupling coefficient is defined for each of all pairs of two Isingspins included in N Ising spins. J_(ij) represents a couplingcoefficient that represents the interaction between the i-th Ising spinand the j-th Ising spin.

h_(i) is the i-th element in the h vector. In the Ising model, anexternal magnetic field coefficient representing an external magneticfield that individually affects each of N Ising spins is defined. h_(i)represents an external magnetic field coefficient that affects the i-thIsing spin.

The Ising problem having a size of N refers to a problem of calculatingspin arrangement that minimizes the Ising energy for the Ising modelincluding N Ising spins. The spin arrangement (S vector) that minimizesthe energy is called the ground state.

FIG. 2 illustrates a graph representing the Ising model when N=6. Agraph vertex corresponds to the Ising spin. A graph edge corresponds tothe coupling coefficient J_(ij) between the Ising spins. The externalmagnetic field coefficient h_(i) is allocated to the graph vertex.

A general combinatorial optimization problem is represented as an Isingproblem defined by the J matrix and the h vector. The Ising machine 12receives the J matrix and h vector as the problem to be solved,internally searches for spin arrangement that implements lower Isingenergy, and outputs the optimized spin arrangement as a solution.

Spin arrangement that implements minimum Ising energy corresponds to anexact solution. Spin arrangement that implements near-minimum Isingenergy corresponds to an approximate solution. In general, theperformance of the Ising machine 12 is expressed by the time required tooutput the solution and the accuracy of the solution (the lower theenergy, the higher the accuracy of the solution). The Ising machine 12may output not only an exact solution but also an approximate solutionas a solution. Further, the search process for searching for the groundstate includes not only a process for searching for an exact solutionbut also a process for searching for an approximate solution, the searchprocess being performed by the Ising machine 12.

In addition, the Ising machine 12 capable of solving the Ising problemhaving a size of N can also solve the Ising problem having a sizesmaller than N. For example, the Ising machine 12 can search for theIsing problem having a size smaller than N as the Ising problem having asize of N by setting, to 0, a coupling coefficient and external magneticfield coefficient of an element without the Ising spin in the J matrixand h vector.

Conventionally, a simulated annealing (SA) method has been known as amethod for solving the Ising problem. A device that performs a searchprocess for the ground state of the Ising model according to the SAmethod is called an SA-based Ising machine.

Further, a simulated bifurcation (SB) method has been known as asolution for solving the Ising problem. The Ising machine 12 alsoperforms the search process for the ground state of the Ising model byusing the simulated bifurcation method. For example, the simulatedbifurcation method has been proposed by Hayato Goto, Kosuke Tatsumura,Alexander R. Dixon, “Combinatorial optimization by simulating adiabaticbifurcations in nonlinear Hamiltonian systems”, Science Advances, Vol.5, no. 4, eaav2372, 19 Apr. 2019, JP 2019-145010 A, JP 2019-159566 A, JP2020-046715 A, JP 2020-046766 A, JP 2020-046784 A, JP 2020-046887 A, andthe like. The simulated bifurcation method is an algorithm in which theequation of motion in an optimization algorithm based on an adiabaticchange in classical mechanics is modified into a form suitable forhigh-speed simulation. The Ising machine 12 performs the search processfor the ground state of the Ising model by using such a simulatedbifurcation method.

The simulated bifurcation method uses two variables, a main variable(x_(i)) and an auxiliary variable (p_(i)), each of which corresponds toN virtual particles. N particles correspond to N Ising spins. In thesimulated bifurcation method, the main variable (x_(i)) represents theposition of the i-th particle among N particles (i=1, 2, . . . , N). Inthe simulated bifurcation method, the auxiliary variable (p_(i))represents the momentum of the i-th particle. Each of N main variables(x_(i)) and each of N auxiliary variables (p_(i)) are continuousvariables represented by real numbers.

Further, in the simulated bifurcation method, for each of N virtualparticles, for example, simultaneous ordinary differential equations ofthe following Equations (2) and (3) are numerically solved.

$\begin{matrix}{\frac{{dx}_{i}}{dt} = {\frac{\partial H}{\partial p_{i}} = {Dp}_{i}}} & (2)\end{matrix}$ $\begin{matrix}{\frac{{dp}_{i}}{dt} = {{- \frac{\partial H}{\partial x_{i}}} = {{\{ {{- D} + {p(t)} - {Kx_{i}^{2}}} \} x_{i}} - {{ch}_{i}{\alpha(t)}} + {c{\sum\limits_{j = 1}^{N}{J_{i,j}x_{j}}}}}}} & (3)\end{matrix}$

Here, H is the Hamiltonian of the following Equation (4).

$\begin{matrix}{H = {\sum\limits_{i = 1}^{N}\lbrack {{\frac{D}{2}( {x_{i}^{2} + p_{i}^{2}} )} - {\frac{p(t)}{2}x_{i}^{2}} + {\frac{K}{4}x_{i}^{4}} + {{ch}_{i}x_{i}{\alpha(t)}} - {\frac{c}{2}{\sum\limits_{j = 1}^{N}{J_{i,j}x_{i}x_{j}}}}} \rbrack}} & (4)\end{matrix}$

c is a predetermined coefficient. D is a predetermined coefficient andcorresponds to detuning. K is a coefficient corresponding to a positiveKerr coefficient. t is a variable that represents the time. p(t)corresponds to the pumping amplitude and is a function of which valuemonotonously increases according to the number of times of update at thetime of calculation in the simulated bifurcation method. An initialvalue of p(t) may be set to 0. α(t) is a function that monotonicallyincreases with p(t).

Here, the symplectic Euler method can be used to solve the differentialequations given by Equations (2) and (3). As shown in the followingEquations (5) and (6), the differential equation is rewritten into adiscrete recurrence formula in a case where the symplectic Euler methodis used.

$\begin{matrix}{x_{i} = {x_{i} + {{Dp}_{i}\Delta t}}} & (5)\end{matrix}$ $\begin{matrix}{p_{i} = {p_{i} + {\{ {{\lbrack {{- D} + {p(t)} - {Kx_{i}^{2}}} \rbrack x_{i}} - {{ch}_{i}{\alpha(t)}} + {c{\sum\limits_{j = 1}^{N}{J_{ij}x_{j}}}}} \}\Delta t}}} & (6)\end{matrix}$

Δt is a time step (unit time or time increment).

Therefore, the Ising machine 12 alternately performs calculation ofEquations (5) and (6) while increasing t by Δt until t reaches apredetermined end time (T). Then, the Ising machine 12 outputs, as asearch result, values of N Ising spins (s_(i)) obtained by binarizingeach of the finally obtained N main variables (x_(i)), or the values ofN main variables (x_(i)).

Note that the Ising machine 12 may perform an algorithm for calculatingan equation other than Equations (3) and (4), as long as the algorithmuses the simulated bifurcation method. For example, the Ising machine 12may perform an algorithm for calculating an equation obtained bymodifying Equations (3) and (4). Further, for example, the Ising machine12 may perform an algorithm for performing a predetermined controlprocess in addition to calculation of Equations (3) and (4) orcalculation of an equation obtained by modifying Equations (3) and (4).

As the Ising machine 12 changes the algorithm to be performed,performance indicators such as a convergence speed and resultingsolution accuracy may change. Therefore, the algorithm applied to theIsing machine 12 may vary depending on the Ising problem to be solvedand the purpose (putting emphasis on the convergence speed, accuracy, orthe like). The Ising machine 12 may perform the search process by usingan algorithm selected by a user among a plurality of preset algorithms.For example, when the Ising machine 12 is a reconfigurable semiconductordevice, the host unit 14 reconfigures the semiconductor device based oncircuit information indicating a circuit that performs the algorithmselected by the user. As a result, the Ising machine 12 can perform thesearch process for the ground state of the Ising model by using anappropriate circuit according to the Ising problem to be solved and thepurpose.

FIG. 3 is a diagram illustrating variables stored in the Ising machine12. The Ising machine 12 performs an algorithm using the simulatedbifurcation method by using a hardware circuit. When performing thesearch process for the ground state of the Ising model including N Isingspins, the Ising machine 12 stores N main variables (x_(i)) and Nauxiliary variables (p_(i)) in an internal memory or register.

As such, the Ising machine 12 stores 2×N variables therein. Therefore,the Ising machine 12 has a different configuration from the SA-basedIsing machine that stores N variables. Note that the main variable(x_(i)) is converted into the Ising spin (s_(i)) by a binarizationprocess. In contrast, the auxiliary variable (p_(i)) is not used forconversion into the Ising spin (s_(i)).

Further, each of N main variables (x_(i)) and each of N auxiliaryvariables (p_(i)) are initialized at the start of the search process.The Ising machine 12 may output different (approximate) solutions in acase where the initial value of the auxiliary variable (p_(i)) isdifferent, even for problems with the same J matrix and h vector.Therefore, the Ising machine 12 can obtain a more accurate solution bychanging the initial value of the auxiliary variable (p_(i)) andperforming the search process for the problems with the same J matrixand h vector.

FIG. 4 is a flowchart illustrating a flow of the search processperformed by the Ising machine 12. The Ising machine 12 performs thesearch process according to the flow illustrated in FIG. 4 .

First, at S111, the Ising machine 12 performs a setting process.Specifically, the Ising machine 12 sets, for example, coefficients of Kand D, functions such as p(t) and α(t), and the number of repetitions.Further, the Ising machine 12 sets the J matrix and the h vector basedon the definition information received from the host unit 14.

Next, at S112, the Ising machine 12 initializes the value of each of Nmain variables (x₁ to x_(N)) and the value of each of N auxiliaryvariables (p₁ to p_(N)). For example, the Ising machine 12 sets thevalue of each of N main variables (x₁ to x_(N)) to 0, a predeterminedvalue, or a value determined by a random number within a predeterminedrange. Further, in a case where the Ising machine 12 receives theinitial value of each of N main variables (x₁ to x_(N)) from the hostunit 14, the Ising machine 12 sets the value of each of N main variables(x₁ to x_(N)) to the initial value received from the host unit 14.Further, the Ising machine 12 sets the value of each of N auxiliaryvariables (p₁ to p_(N)) to the initial value received from the host unit14.

Next, the Ising machine 12 repeats a loop process from S113 to S120 aset number of times.

At S114 to S116 in the loop, the Ising machine 12 performs an auxiliaryvariable update process while incrementing i by 1 from i=1 to i=N (S114,S115, and S116). In the auxiliary variable update process (S115) forupdating the i-th auxiliary variable, the Ising machine 12 updates thei-th auxiliary variable (p_(i)) by N main variables (x_(i) to x_(N)), Ncoupling coefficients (J_(i,j)) representing the interaction between thei-th main variable (x_(i)) and the remaining (N−1) main variables(x_(1 to i−1) and x_(i+1 to N)), and the i-th external magnetic fieldcoefficient (h_(j)).

Specifically, the Ising machine 12 calculates the i-th auxiliaryvariable (p_(i)) by calculating Equation (6) described above.

Note that the Ising machine 12 may perform the process of S115 inparallel. As a result, the Ising machine 12 can calculate N auxiliaryvariables (p_(i) to p_(N)) at high speed.

Next, at S117 to S119, the Ising machine 12 performs a main variableupdate process while incrementing i by 1 from i=1 to i=N (S117, S118,and S119). In the main variable update process (S118) for updating thei-th main variable, the Ising machine 12 updates the i-th main variable(x_(i)) by the i-th auxiliary variable (p_(i)).

Specifically, the Ising machine 12 calculates the i-th main variable(x_(i)) by calculating Equation (5) described above.

Note that the Ising machine 12 may perform the process of S118 inparallel. As a result, the Ising machine 12 can calculate N mainvariables (x_(i) to x_(N)) at high speed.

Then, when the loop process between S113 and S120 is performed a setnumber of times, the Ising machine 12 proceeds to S121. Note that, inthe loop process from S113 to S120, the Ising machine 12 may perform theprocess of S117 to S119 first and the process of S114 to S116 later.

At S121, the Ising machine 12 outputs a search result to the host unit14. For example, the Ising machine 12 outputs, to the host unit 14, NIsing spins (s₁ to 5N) obtained by binarizing each of N main variables(x₁ to x_(N)) or N main variables (x₁ to x_(N)). Then, when the processof S121 is completed, the Ising machine 12 ends the search process.

As described above, for each of N Ising spins (s₁ to s_(N)), the Isingmachine 12 alternately repeats the auxiliary variable update process(S115) for updating the auxiliary variable by the main variable and themain variable update process (S118) for updating the main variable bythe auxiliary variable multiple times. Further, the Ising machine 12outputs, as the search result, a value based on the main variable afterthe auxiliary variable update process (S115) and the main variableupdate process (S118) are alternately performed multiple times. As aresult, the Ising machine 12 can perform the search process for theground state of the Ising model by performing an algorithm using thesimulated bifurcation method.

FIG. 5 is a diagram illustrating an example of a hardware configurationof the information processing system 10. For example, the informationprocessing system 10 includes an FPGA 32, a central processing unit(CPU) 34, a main storage device 36, a circuit information storage device38, an input device 40, a display device 42, and a bus 44.

The FPGA 32 receives circuit information from the CPU 34 via the bus 44,and is configured as a circuit predetermined according to the receivedcircuit information. As a result, the FPGA 32 functions as the Isingmachine 12.

The FPGA 32 receives the definition information and the controlparameter from the CPU 34 via the bus 44, and performs the searchprocess according to the received definition information and controlparameter. The definition information is information that defines theIsing model. Specifically, the definition information is the J matrixand the h vector. The control parameter is information for controllingthe search process. For example, the control parameter is a coefficient(c, D, or K), a function (α(t) or p(t)), a unit time (Δt), or the numberof repetitions of the loop process.

Further, prior to the search process, the FPGA 32 receives, from the CPU34 via the bus 44, the initial value of each of N auxiliary variables(p_(i)) corresponding to the plurality of Ising spins included in theIsing model, the initial value being stored in the main storage device36. Moreover, prior to the search process, the FPGA 32 may receive, fromthe CPU 34 via the bus 44, the initial value of each of N main variables(x_(i)) corresponding to the plurality of Ising spins, the initial valuebeing stored in the main storage device 36.

Then, after the search process is completed, the FPGA 32 outputs thesearch result to the host unit 14 via the bus 44. Specifically, the FPGA32 outputs, as the search result, the value of the Ising spin (s_(i))obtained by binarizing each of the main variables (x_(i)) correspondingto each of the plurality of Ising spins, or the value of each of theplurality of main variables (x_(i)) to the host unit 14.

The CPU 34 is operated according to a program stored in the main storagedevice 36. As a result, the CPU 34 and the main storage device 36function as the host unit 14.

The CPU 34 performs a preprocess, a parameter transmission process, aresult reception process, and a main process. The CPU 34 generates thedefinition information and the control parameter in the preprocess. Inaddition, the CPU 34 generates the initial value of each of theplurality of auxiliary variables (p_(i)) in the preprocess. The CPU 34may further generate the initial value of each of the plurality of mainvariables (x_(i)) in the preprocess.

In the parameter transmission process, the CPU 34 transmits thedefinition information, the control parameter, and the initial value ofeach of the plurality of auxiliary variables (p_(i)) to the FPGA 32 viathe bus 44. In the parameter transmission process, the CPU 34 mayfurther transmit the initial value of each of the plurality of mainvariables (x_(i)) to the FPGA 32 via the bus 44.

In the result reception process, the CPU 34 receives the search resultfrom the FPGA 32 via the bus 44, and outputs the solution of thecombinatorial optimization problem based on the received search result.Further, the CPU 34 performs, as the main process, a process other thanthe preprocess, the parameter transmission process, and the resultreception process.

The main storage device 36 is a random access memory (RAM). The mainstorage device 36 is used as a work area for data processing of the CPU34.

The circuit information storage device 38 is a non-volatile storagedevice. The circuit information storage device 38 stores circuitinformation for configuring the FPGA 32 as a circuit for searching forthe ground state of the Ising model.

The circuit information storage device 38 may store a plurality ofcircuit informations. The plurality of respective circuit informationsmay be, for example, informations indicating circuits that the maximumsizes of the Ising model that can be solved are different from eachother. Further, the plurality of respective circuit information may be,for example, information indicating circuits that perform the searchprocess using algorithms different from each other. The CPU 34 selectscircuit information specified by the user among the plurality of circuitinformations, and reconfigures the FPGA 32 according to the selectedcircuit information.

The input device 40 is a device for inputting an instruction or the likefrom the user. The input device 40 is, for example, a mouse, a keyboard,or the like. The input device 40 receives a process start instructionfrom the user. When the input device 40 receives the start instructionfrom the user, the CPU 34 starts the process for calculating thesolution of the combinatorial optimization problem.

The display device 42 is a device for displaying information to theuser. The display device 42 displays the solution of the combinatorialoptimization problem.

The bus 44 connects the FPGA 32, the CPU 34, the main storage device 36,the circuit information storage device 38, the input device 40, and thedisplay device 42 to transmit and receive data. The bus 44 functions asan interface connecting the Ising machine 12 and the host unit 14.

FIG. 6 is a sequence diagram illustrating a process flow of theinformation processing system 10. In a case where the FPGA 32 calculatesthe solution of the Ising model including N Ising spins, the informationprocessing system 10 performs the process according to the flowillustrated in FIG. 6 .

First, at S11, the CPU 34 performs the main process. Next, at S12, theCPU 34 performs the preprocess. Specifically, in the preprocess, the CPU34 generates the definition information (J and h), the controlparameter, and the initial value of each of N auxiliary variables (p₁ toP_(N)) in association with the Ising machine 12 configured in the FPGA32. Further, the CPU 34 may generate the initial value of each of N mainvariables (x₁ to x_(N)).

Next, at S13, the CPU 34 transmits, to the FPGA 32 via the bus 44, thedefinition information (J and h), the control parameter, and the initialvalue of each of N auxiliary variables (p₁ to P_(N)). Further, the CPU34 may transmit the initial value of each of N main variables (x₁ tox_(N)) to the FPGA 32 via the bus 44.

Next, at S14, the FPGA 32 performs the search process. Specifically, foreach of N Ising spins, the FPGA 32 alternately repeats the auxiliaryvariable update process for updating the auxiliary variable (p_(i)) bythe main variable (x_(i)) and the main variable update process forupdating the main variable (x_(i)) by the auxiliary variable (p_(i))multiple times. Specifically, the FPGA 32 performs the processillustrated in FIG. 4 .

Note that, at the start of the search process, the FPGA 32 sets theinitial value received from the CPU 34 for each of N auxiliary variables(p_(i)). Further, at the start of the search process, the FPGA 32 sets apredetermined value such as 0 as the initial value for each of N mainvariables (x_(i)).

Further, the FPGA 32 may internally generate a value corresponding to arandom number or the like as the initial value and set the generatedvalue for each of N main variables (x_(i)). Note that in a case wherethe FPGA 32 receives the initial value of each of N main variables(x_(i)) from the CPU 34, the FPGA 32 sets the initial value receivedfrom the CPU 34 for each of N main variables (x_(i)).

Next, at S14, the FPGA 32 transmits a search result to the CPU 34.Specifically, the FPGA 32 transmits, to the CPU 34 via the bus 44, NIsing spins (s₁ to s_(N)) obtained by binarizing each of N mainvariables (x₁ to x_(N)), or N main variables (x₁ to x_(N)). Next, atS15, the CPU 34 receives the search result from the FPGA 32 via the bus44.

As described above, in the information processing system 10 according tothe present embodiment, in addition to the definition information (J andh) that defines the Ising model, and the control parameter, the initialvalue of each of the plurality of auxiliary variables (p_(i)) istransmitted from the host unit 14 (the CPU 34 and the main storagedevice 36) to the Ising machine 12 (the FPGA 32) via the interface (thebus 44). The Ising machine 12 (the FPGA 32) can output a differentapproximate solution in a case where the initial value of the auxiliaryvariable (p_(i)) is different, even when the value of the main variable(x_(i)) is fixed. That is, even in a case where the host unit 14 (theCPU 34) does not transmit the initial value of the main variable (x_(i))to the Ising machine 12 (the FPGA 32), when the initial value of theauxiliary variable (p_(i)) is changed, the Ising machine 12 (the FPGA32) can perform an appropriate search process. Therefore, theinformation processing system 10 according to the present embodimentdoes not need to generate and transmit the main variable (x_(i)), andcan shorten the process time and the communication time. As describedabove, with the information processing system 10 according to thepresent embodiment, the solution of the combinatorial optimizationproblem can be calculated at high speed.

Second Embodiment

Next, an information processing system 10 according to a secondembodiment will be described. The information processing system 10according to the second embodiment has almost the same configuration asthat of the first embodiment. Therefore, in the description of theinformation processing system 10 according to the second embodiment, thesame components as those of the first embodiment are designated by thesame reference signs, and a detailed description thereof will beomitted.

The information processing system 10 according to the second embodimentsolves a plurality of combinatorial optimization problems one by one.

FIG. 7 is a diagram illustrating a hardware configuration of theinformation processing system 10 according to the second embodiment. ACPU 34 according to the second embodiment includes a first flag storagecircuit 51. The first flag storage circuit 51 stores a first flagindicating whether or not a search process performed by an FPGA 32 iscompleted. The first flag storage circuit 51 is, for example, a flagregister provided in the CPU 34. The first flag storage circuit 51 maybe provided outside the CPU 34 (for example, a main storage device 36).

The CPU 34 can write and read the first flag in and from the first flagstorage circuit 51. At the same time, the first flag is set in the firstflag storage circuit 51 according to an operating state of the FPGA 32.For example, the first flag of 0 indicates that the search processperformed by the FPGA 32 is not completed, and the first flag of 1indicates that the search process performed by the FPGA 32 is completed.

Further, in the second embodiment, instead of the FPGA 32, the CPU 34can also perform the search process. In this case, the CPU 34 performsthe search process by executing a predetermined search program.

FIG. 8 is a flowchart illustrating a process flow of the CPU 34according to a first example of the second embodiment. In the firstexample, in the information processing system instead of the FPGA 32,the CPU 34 performs the search process. In the first example, the CPU 34performs the process according to the flow illustrated in FIG. 8 .

In the first example, the CPU 34 performs loop process between S21 andS24 L times. L represents the number of combinatorial optimizationproblems to be solved and is a predetermined integer of 2 or more. TheCPU 34 performs the main process (S22) and the search process (S23) ineach loop process. Note that the main process (S22) is the same as theprocess of S11 illustrated in FIG. 6 . Further, the search process (S23)is the same as the process of S14 illustrated in FIG. 6 . Then, when theloop process is performed L times, the CPU 34 ends this flow (S24).

FIG. 9 is a timing chart of the process performed by the informationprocessing system 10 according to the first example of the secondembodiment. m represents an index of the combinatorial optimizationproblem to be solved and is an integer from 1 to L. The informationprocessing system 10 sequentially solves the combinatorial optimizationproblem of m=1 to the combinatorial optimization problem of m=L whileincrementing m by 1.

As illustrated in FIG. 9 , in the first example, the CPU 34 alternatelyrepeats the main process and the search process. As a result, theinformation processing system 10 according to the first example of thesecond embodiment can sequentially solve a plurality of combinatorialoptimization problems.

FIG. 10 is a flowchart illustrating a process flow of the CPU 34according to a second example of the second embodiment. In the secondexample, in the information processing system 10, the FPGA 32 performsthe search process, and the CPU 34 performs a process other than thesearch process. In the second example, the CPU 34 performs the processaccording to the flow illustrated in FIG. 10 .

In the second example, the CPU 34 performs loop process between S31 andS41 L times. The CPU 34 performs the processes from S32 to S40 in eachloop process.

At S32, the CPU 34 performs a main process. The main process (S32) isthe same as the process of S11 illustrated in FIG. 6 . Next, at S33, theCPU 34 performs a preprocess. The preprocess of S33 will be describedlater with reference to FIG. 11 .

Next, at S34, the CPU 34 determines whether or not to reconfigure theFPGA 32. For example, the CPU 34 determines whether or not a circuitcurrently configured in the FPGA 32 supports the Ising model thatrepresents the combinatorial optimization problem to be solved. Then, ina case where the circuit supports the Ising model, the CPU 34 determinesnot to perform the reconfiguration, and in a case where the circuit doesnot support the Ising model, the CPU 34 determines to perform thereconfiguration. In a case where the reconfiguration is not performed(No at S34), the CPU 34 proceeds to S36. In a case where thereconfiguration is performed (Yes at S34), the CPU 34 proceeds to S35.At S35, the CPU 34 provides, to the FPGA 32, circuit informationcorresponding to the Ising model representing the combinatorialoptimization problem to be solved, and reconfigures the FPGA 32.

Next, at S36, the CPU 34 transmits a parameter generated in thepreprocess (S33) to the FPGA 32. Specifically, the CPU 34 transmits, tothe FPGA 32 via a bus 44, the definition information (J and h), thecontrol parameter, and the initial value of each of N auxiliaryvariables (p₁ to p_(N)). Further, the CPU 34 may transmit the initialvalue of each of N main variables (x₁ to x_(N)) to the FPGA 32 via thebus 44.

Next, at S37, the CPU 34 instructs the FPGA 32 to start the searchprocess. Note that, prior to the start of the search process, the FPGA32 sets the first flag (bs_flag) to 0 which is a value indicating thatthe search process is not completed. Further, when the search process iscompleted, the FPGA 32 sets the first flag (bs_flag) to 1 which is avalue indicating that the search process is completed.

Next, at S38, the CPU 34 checks whether or not the search processperformed by the FPGA 32 is completed. Specifically, the CPU 34 acquiresthe first flag (bs_flag).

Next, at S39, the CPU 34 determines whether or not the search process iscompleted. In a case where the search process is completed, that is, ina case where bs_flag is 1 (bs_flag==1) (Yes at S39), the CPU 34 proceedsto S40. In a case where the search process is not completed, that is, ina case where bs_flag is not 1 (No at S39), the CPU 34 returns to S38 andrepeats the process of S38 and S39. That is, the CPU 34 performspolling, which is a process for repeatedly checking the first flag(bs_flag) in order to confirm that the search process is completed, fromwhen the CPU 34 instructs the start of the search process to when thesearch process is completed.

At S40, the CPU 34 receives a search result from the FPGA 32. Then, whenthe loop process is performed L times, the CPU 34 ends this flow (S41).

FIG. 11 is a flowchart illustrating a flow of the preprocess (S33). TheCPU 34 performs the processes from S51 to S54 in the preprocess (S33).

At S51, the CPU 34 generates the initial value of each of N auxiliaryvariables (p₁ to p_(N)). Note that the CPU 34 may further generate theinitial value of each of N main variables (x_(i)).

Next, at S52, the CPU 34 generates the J matrix. Next, at S53, the CPU34 generates the h vector. Next, at S54, the CPU 34 generates thecontrol parameter such as a coefficient (c, D, or K), a function (α(t)or p(t)), a unit time (Δt), or the number of repetitions. When theprocess of S54 is completed, the CPU 34 returns to the flow of FIG. 10 .

FIG. 12 is a timing chart of the process performed by the informationprocessing system 10 according to the second example of the secondembodiment. As illustrated in FIG. 12 , in the second example of thesecond embodiment, after the CPU 34 performs the main process, thepreprocess, and the parameter transmission process, the FPGA 32 performsthe search process. While the FPGA 32 performs the search process, theCPU 34 checks, by polling, whether or not the search process iscompleted, and performs the result reception process after the searchprocess is completed. Then, the CPU 34 starts the main process of thenext problem after the result reception process is performed. Asdescribed above, in the information processing system 10 according tothe second example of the second embodiment, the CPU 34 and the FPGA 32perform the process at an exclusive timing. As a result, the informationprocessing system 10 according to the second example of the secondembodiment can sequentially solve a plurality of combinatorialoptimization problems.

Here, the FPGA 32 can configure a circuit that calculates N mainvariables (x₁ to x_(N)) and N auxiliary variables (p₁ to P N) inparallel. Therefore, the FPGA 32 can perform large-scale parallelcalculation. On the other hand, in general, the CPU 34 cannot performlarge-scale parallel calculation, because the number of cores and thenumber of threads are limited. Therefore, although the preprocess, theparameter transmission process, and the result reception process areadditionally performed in the information processing system 10 accordingto the second example, the search process can be significantlyshortened, as compared with the information processing system 10according to the first example. Therefore, the information processingsystem 10 according to the second example can increase the throughput asa whole.

Third Embodiment

Next, an information processing system 10 according to a thirdembodiment will be described. The information processing system 10according to the third embodiment has almost the same configuration asthat of the second embodiment. Therefore, in the description of theinformation processing system 10 according to the third embodiment, thesame components as those of the second embodiment are designated by thesame reference signs, and a detailed description thereof will beomitted.

The information processing system 10 according to the third embodimentsequentially solves a plurality of combinatorial optimization problemsone by one, and in the information processing system 10 according to thethird embodiment, the main process and the search process are performedby a CPU 34 and an FPGA 32, respectively, in parallel.

FIG. 13 is a diagram illustrating a functional configuration of theinformation processing system 10 according to the third embodiment. TheCPU 34 according to the third embodiment further includes a second flagstorage circuit 52, which is different from the configuration of thesecond embodiment illustrated in FIG. 7 . The second flag storagecircuit 52 stores a second flag indicating whether or not the CPU 34 hasreceived a search result from the FPGA 32. The second flag storagecircuit 52 is, for example, a flag register provided in the CPU 34. Thesecond flag storage circuit 52 may be provided outside the CPU 34 (forexample, a main storage device 36).

The CPU 34 can perform writing and reading with respect to the secondflag storage circuit 52. For example, the second flag of 0 indicatesthat the CPU 34 has not received the search result, and the second flagof 1 indicates that the CPU 34 has received the search result.

FIG. 14 is a flowchart illustrating a process flow of the CPU 34according to the third embodiment. The CPU 34 according to the thirdembodiment performs the process according to the flow illustrated inFIG. 14 .

First, at S61, the CPU 34 sets a first flag (bs_flag) to which is avalue indicating that the search process is not completed. Further, theCPU 34 sets the second flag (rcv_flag) to 1 which is a value indicatingthat the search result has been received.

Next, the CPU 34 performs loop process between S62 and S75 L times. TheCPU 34 performs the processes from S63 to S74 in each loop process.

At S63, the CPU 34 enables a timer interrupt. A timer generates a timerflag at predetermined time intervals. When the timer interrupt isenabled, the CPU 34 performs the process illustrated in FIG. 15 asdescribed later each time the timer flag is generated.

Next, at S64, the CPU 34 performs the main process. The main process(S64) is the same as the process of S32 illustrated in FIG. 10 .

Next, at S65, the CPU 34 performs the preprocess. The preprocess (S65)is the same as the process of S33 illustrated in FIG. 10 .

Next, at S66, the CPU 34 disables the timer interrupt enabled at S63.Thereafter, the CPU 34 does not perform the process illustrated in FIG.15 even when the timer flag is generated, until the timer interrupt isenabled again.

Next, at S67, the CPU 34 determines whether or not the second flag(rcv_flag) indicates that a search result has not been received. In acase where the second flag (rcv_flag) indicates that the search resulthas been received, that is, in a case where rcv_flag is not 0 (No atS67), the CPU 34 proceeds to S71. In a case where the second flag(rcv_flag) indicates that the search result has not been received, thatis, in a case where rcv_flag is 0 (rcv_flag==0) (Yes at S67), the CPU 34proceeds to S68.

Next, at S68, the CPU 34 checks whether or not the search processperformed by the FPGA 32 is completed. Specifically, the CPU 34 acquiresthe first flag (bs_flag).

Next, at S69, the CPU 34 determines whether or not the search process iscompleted. In a case where the search process is completed, that is, ina case where bs_flag is 1 (bs_flag==1) (Yes at S69), the CPU 34 proceedsto S70. In a case where the search process is not completed, that is, ina case where bs_flag is not 1 (No at S69), the CPU 34 returns to S68 andrepeats the process of S68 and S69. That is, the CPU 34 performs pollingfor confirming that the search process is completed, from when the CPU34 instructs the start of the search process to when the search processis completed.

At S70, the CPU 34 receives a search result from the FPGA 32. Further,the CPU 34 sets the second flag (rcv_flag) to 1 which is a valueindicating that the search result has been received, when the receptionof the search result is completed.

Next, at S71, the CPU 34 determines whether or not to reconfigure theFPGA 32. In a case where the reconfiguration is not performed (No atS71), the CPU 34 proceeds to S73. In a case where the reconfiguration isperformed (Yes at S71), the CPU 34 proceeds to S72. At S72, the CPU 34provides, to the FPGA 32, circuit information corresponding to the Isingmodel representing the combinatorial optimization problem to be solved,and reconfigures the FPGA 32.

Next, at S73, the CPU 34 transmits a parameter generated in thepreprocess (S65) to the FPGA 32. The parameter transmission process(S73) is the same as the process of S36 illustrated in FIG. 10 .

Next, in S74, the CPU 34 instructs the FPGA 32 to start the searchprocess. Further, the CPU 34 sets the second flag (rcv_flag) to 0 whichis a value indicating that the search result has not been received.Then, when the loop process is performed L times, the CPU 34 ends thisflow (S75).

FIG. 15 is a flowchart illustrating a process flow when the timerinterrupt occurs in the CPU 34 according to the third embodiment. TheCPU 34 according to the third embodiment performs the process accordingto the flow illustrated in FIG. 15 when the timer interrupt occurs in astate where the timer interrupt is enabled.

First, at S81, the CPU 34 determines whether or not the second flag(rcv_flag) indicates that a search result has not been received. In acase where the second flag (rcv_flag) indicates that the search resulthas been received, that is, in a case where rcv_flag is not 0 (No atS81), the CPU 34 ends the flow of the timer interrupt. In a case wherethe second flag (rcv_flag) indicates that the search result has not beenreceived, that is, in a case where rcv_flag is 0 (rcv_flag==0) (Yes atS81), the CPU 34 proceeds to S82.

At S82, the CPU 34 checks whether or not the search process performed bythe FPGA 32 is completed. Specifically, the CPU 34 acquires the firstflag (bs_flag).

Next, at S83, the CPU 34 determines whether or not the search process iscompleted. In a case where the search process is completed, that is, ina case where bs_flag is 1 (bs_flag==1) (Yes at S83), the CPU 34 proceedsto S84. In a case where the search process is not completed, that is, ina case where bs_flag is not 1 (No at S83), the CPU 34 ends the flow ofthe timer interrupt.

At S84, the CPU 34 receives a search result from the FPGA 32. Further,the CPU 34 sets the second flag (rcv_flag) to 1 which is a valueindicating that the search result has been received, when the receptionof the search result is completed. Then, when the process of S84 iscompleted, the CPU 34 ends the flow of the timer interrupt.

FIG. 16 is a timing chart of the process performed by the informationprocessing system 10 according to the third embodiment. In theinformation processing system 10 according to the third embodiment, theCPU 34 performs the main process for the combinatorial optimizationproblem to be solved next during the search process performed by theFPGA 32. For example, in the information processing system 10, in a casewhere a first search process (m=1) for searching for the ground state ofa first Ising model is performed, and then a second search process (m=2)for searching for the ground state of a second Ising model is performed,the CPU 34 and the FPGA 32 perform processes as follows.

First, the CPU 34 performs a first main process for generatinginformation used for performing the first search process (m=1), and thenperforms a preprocess and a parameter transmission process for the firstsearch process (m=1). Next, the FPGA 32 performs the first searchprocess (m=1) after the first main process is performed by the CPU 34.

Next, the CPU 34 performs a second main process for generatinginformation used for performing the second search process (m=2) during aperiod in which the FPGA 32 performs the first search process (m=1). Ina case where the first search process (m=1) performed by the FPGA 32 iscompleted while the second main process is performed, the CPU 34temporarily suspends the second main process and performs a resultreception process for receiving a search result of the first searchprocess (m=1). Then, the FPGA 32 performs the second search process(m=2) after the second main process is performed by the CPU 34.

As such, the information processing system 10 according to the thirdembodiment operates the CPU 34 and the FPGA 32 in parallel. As a result,the information processing system 10 according to the third embodimentcan shorten the overall process time and increase the throughput as awhole.

Fourth Embodiment

Next, an information processing system 10 according to a fourthembodiment will be described. The configuration of the informationprocessing system 10 according to the fourth embodiment is the same asthe configuration of the information processing system 10 according tothe third embodiment illustrated in FIG. 13 . Further, a process of theinformation processing system 10 according to the fourth embodiment in acase where the timer interrupt occurs is different from that of theinformation processing system 10 according to the third embodiment, andother processes of the information processing system 10 according to thefourth embodiment are the same as those of the information processingsystem 10 according to the third embodiment. Therefore, in thedescription of the information processing system 10 according to thefourth embodiment, the same components as those of the third embodimentare designated by the same reference signs, and a detailed descriptionthereof will be omitted.

The information processing system 10 according to the fourth embodimentsequentially solves a plurality of combinatorial optimization problemsone by one, and in the information processing system 10 according to thefourth embodiment, the main process and the search process are performedby a CPU 34 and an FPGA 32, respectively, in parallel. Further, theinformation processing system 10 according to the fourth embodimentperforms the search process multiple times if possible during the mainprocess of the CPU 34.

FIG. 17 is a flowchart illustrating a process flow when the timerinterrupt occurs in the CPU 34 according to the fourth embodiment. TheCPU 34 according to the fourth embodiment performs the process accordingto the flow illustrated in FIG. 17 when the timer interrupt occurs in astate where the timer interrupt is enabled.

First, at S91, the CPU 34 determines whether or not the second flag(rcv_flag) indicates that a search result has not been received. In acase where the second flag (rcv_flag) indicates that the search resulthas been received, that is, in a case where rcv_flag is not 0 (No atS91), the CPU 34 ends the flow of the timer interrupt. In a case wherethe second flag (rcv_flag) indicates that the search result has not beenreceived, that is, in a case where rcv_flag is 0 (rcv_flag==0) (Yes atS91), the CPU 34 proceeds to S92.

At S92, the CPU 34 checks whether or not the search process performed bythe FPGA 32 is completed. Specifically, the CPU 34 acquires the firstflag (bs_flag).

Next, at S93, the CPU 34 determines whether or not the search process iscompleted. In a case where the search process is completed, that is, ina case where bs_flag is 1 (bs_flag==1) (Yes at S93), the CPU 34 proceedsto S94. In a case where the search process is not completed, that is, ina case where bs_flag is not 1 (No at S93), the CPU 34 ends the flow ofthe timer interrupt.

At S94, the CPU 34 receives a search result from the FPGA 32. Further,the CPU 34 sets the second flag (rcv_flag) to 1 which is a valueindicating that the search result has been received, when the receptionof the search result is completed.

Next, at S95, the CPU 34 generates the initial value of each of Nauxiliary variables (p₁ to p_(N)). Note that the CPU 34 may furthergenerate the initial value of each of N main variables (x₁ to x_(N)).

Here, in the present embodiment, the FPGA 32 can perform the searchprocess multiple times while the main process is performed by the CPU 34one time. At S95, the CPU 34 generates initial values for performing thesecond and subsequent search processes (ini=2 or more) out of aplurality of search processes performed while the main process isperformed one time. At S95, the CPU 34 generates the initial value ofeach of N auxiliary variables (p_(i) to p_(N)) and the initial value ofeach of N main variables (x₁ to x_(N)) so that different values arecombined for each of the plurality of search processes performed duringthe main process.

Next, at S96, the CPU 34 transmits the generated initial value of eachof N auxiliary variables (p₁ to p_(N)) to the FPGA 32. Further, when theCPU 34 generates the initial values of the main variables (x₁ to x_(N)),the CPU 34 transmits the generated initial value of each of N mainvariables (x₁ to x_(N)) to the FPGA 32.

Next, in S97, the CPU 34 instructs the FPGA 32 to start the searchprocess. Further, the CPU 34 sets the second flag (rcv_flag) to 0 whichis a value indicating that the search result has not been received.

When the FPGA 32 receives an instruction to start the search processfrom the CPU 34, the FPGA 32 changes only the initial value of each of Nauxiliary variables (p₁ to p_(N)) and the initial value of each of Nmain variables (x₁ to x_(N)) without changing the definition information(J and h) and the control parameter, and starts the search process.Then, when the process of S97 is completed, the CPU 34 ends the flow ofthe timer interrupt.

FIG. 18 is a timing chart of the process performed by the informationprocessing system 10 according to the fourth embodiment.

In the information processing system 10 according to the fourthembodiment, the CPU 34 performs the main process for the combinatorialoptimization problem to be solved next during the search processperformed by the FPGA 32. Further, the FPGA 32 performs the searchprocess multiple times while changing the initial value of each of Nauxiliary variables (p_(i) to p_(N)) until the CPU 34 ends the mainprocess.

For example, in the information processing system 10, in a case where afirst search process (m=1) for searching for the ground state of a firstIsing model is performed, and then a second search process (m=2) forsearching for the ground state of a second Ising model is performed, theCPU 34 and the FPGA 32 perform processes as follows.

First, the CPU 34 performs the first main process, and then performs thepreprocess and the parameter transmission process for the first searchprocess (m=1). Next, the FPGA 32 performs the first search process(m=1). Next, the CPU 34 performs the second main process during a periodin which the FPGA 32 performs the first search process (m=1).

Here, in a case where the first search process (m=1) performed by theFPGA 32 is completed while the second main process is performed, the CPU34 temporarily suspends the second main process and performs a resultreception process for receiving a search result of the first searchprocess (m=1). Further, the CPU 34 transmits a new initial value of eachof N auxiliary variables (p₁ to p_(N)), and causes the FPGA 32 toperform the first search process again according to the new initialvalue. Then, the CPU 34 causes the FPGA 32 to repeat the first searchprocess until the second main process is completed.

Then, in a case where a plurality of search results of the first searchprocess obtained with different initial values of the auxiliary variableare received while the second main process is performed, the CPU 34generates a search result of the first search process based on theplurality of received search results.

As described above, in the information processing system 10 according tothe fourth embodiment, the CPU 34 and the FPGA 32 are operated inparallel, such that the overall process time can be shortened and thethroughput can be increased as a whole. Further, the informationprocessing system 10 according to the fourth embodiment can acquire aplurality of search results for one combinatorial optimization problemand output the solution based on the plurality of search results. As aresult, the information processing system 10 according to the fourthembodiment can output a more accurate solution.

First Modified Example

Next, a first modified example will be described. The first modifiedexample is applicable to all of the second to fourth embodiments.

The information processing system 10 according to the first modifiedexample solves a plurality of combinatorial optimization problems one byone. Before solving each combinatorial optimization problem, theinformation processing system 10 determines whether or not a circuitcurrently configured in the FPGA 32 is suitable, and in a case where thecircuit is not suitable, the information processing system 10reconfigures the FPGA 32, and in a case where the circuit is suitable,the information processing system 10 performs the process withoutreconfiguring the FPGA 32.

For example, the CPU 34 selects circuit information indicating a circuitthat performs an appropriate algorithm according to a combinatorialoptimization problem to be solved or a purpose (putting emphasis on theconvergence speed, accuracy, or the like) among a plurality of circuitinformations, and reconfigures the FPGA 32 according to the selectedcircuit information. Further, for example, the CPU 34 determines whetheror not to reconfigure the FPGA 32 to shorten the entire process timeincluding the reconfiguration time.

FIG. 19 is a diagram illustrating a process time in a case where theFPGA 32 is not reconfigured and a process time in a case where the FPGA32 is reconfigured. For example, it is assumed that the informationprocessing system 10 executes an application that solves a combinatorialoptimization problem in which the size of the J matrix changesdynamically.

It is assumed that the application solves a large-scale problem(N=N_(large)) in the first process (m=1), and then solves a small-scaleproblem (N=N_(small)) in the second process (m=2). Note thatN_(large)>N_(small). In a case where the reconfiguration is notperformed in the second process (m=2), the FPGA 32 performs the searchprocess for the ground state by using a circuit for solving thelarge-scale problem (N=N_(large)). Therefore, in a case where thereconfiguration is not performed in the second process (m=2), theprocess time is determined by a variable update time for updatingN_(large) main variables and N_(large) auxiliary variables, and thenumber of repetitions of an update process.

In the second process (m=2), the search process in a specified state canbe performed by a circuit for solving the small-scale problem(N=N_(small)). A variable update time of the circuit for solving thesmall-scale problem (N=N_(small)) is shorter than a variable update timeof the circuit for solving the large-scale problem (N=N_(large)).However, the FPGA 32 needs to perform the reconfiguration process in acase of implementing the circuit for solving the small-scale problem(N=N_(small)) in the second process (m=2). That is, in a case where thesum of the process time of the circuit after the reconfiguration and thereconfiguration time is shorter than the previous process time of thecircuit before the reconfiguration, the FPGA 32 can shorten the overallprocess time of the second process (m=2).

Therefore, in a case of performing a search process for searching forthe ground state of the second Ising model that can be searched for by afirst circuit capable of searching for the ground state of the firstIsing model in a state where the first circuit is configured in the FPGA32, the CPU 34 performs the following processes.

First, a first time representing an estimated execution time of thesearch process performed by the first circuit and a second timeincluding a reconfiguration time for reconfiguring the FPGA 32 as thesecond circuit and an estimated execution time of the search processperformed by the second circuit are compared with each other. Here, thesecond circuit is a circuit that can search for the ground state of thesecond Ising model, and of which the search time is shorter than that ofthe first circuit.

Then, in a case where the second time is equal to or longer than thefirst time, the CPU 34 causes the FPGA 32 to perform the search processfor searching for the ground state of the second Ising model withoutreconfiguring the FPGA 32 in which the first circuit is configured. In acase where the second time is shorter than the first time, the CPU 34reconfigures the FPGA 32 as the second circuit and causes the FPGA 32 toperform the search process for searching for the ground state of thesecond Ising model. By performing such a process, the informationprocessing system 10 can shorten the overall process time.

In addition, the information processing system 10 may continuouslysearch for the ground state of one or more Ising models that can searchfor the ground state by using the second circuit after searching for theground state of the second Ising model. In such a case, the CPU 34 adds,to the first time, a predicted execution time in a case where the firstcircuit searches for the ground state of each of one or more Isingmodels following the second Ising model. Further, the CPU 34 adds, tothe second time, a predicted execution time in a case where the secondcircuit searches for the ground state of each of one or more Isingmodels following the second Ising model. As a result, the informationprocessing system 10 can shorten the overall process time even in a casewhere the second circuit continuously searches for the ground states ofa plurality of Ising models.

Second Modified Example

Next, a second modified example will be described. The second modifiedexample is applicable to all of the first to fourth embodiments.

FIG. 20 is a diagram illustrating coupling information including acoupling coefficient. In the second modified example, the informationprocessing system 10 acquires, from the user or the like, definitioninformation that defines the Ising model representing the combinatorialoptimization problem to be solved. The definition information includesthe coupling information in which a plurality of coupling coefficientsthat define the Ising model are described. For example, the informationprocessing system 10 acquires filed coupling information described in apredetermined format.

Each of the plurality of coupling coefficients included in the couplinginformation is associated with an index for specifying the i-th and anindex for specifying the j-th. Further, for example, in the couplinginformation, a plurality of coupling coefficients are described side byside in raster scan order of the indexes of i and j. Therefore, the CPU34 can detect the size of the J matrix from the indexes (i and j) of thecoupling coefficient at the final position. For example, in the exampleof FIG. 20 , the CPU 34 detects N=4 as the size of the Ising model bydetecting N max (i,j). Note that max 0 is a function that detects themaximum values of i and j among a plurality of coupling coefficientsincluded in the coupling information.

Prior to the search process for the combinatorial optimization problem,the CPU 34 selects appropriate circuit information from a plurality ofcircuit informations stored in the circuit information storage device38, and provides the selected circuit information to the FPGA 32 toconfigure a circuit in the FPGA 32. In this case, the CPU 34 selects thecircuit information based on the size of the Ising model detected fromcoefficient information. For example, the CPU 34 selects circuitinformation indicating a circuit that searches for an Ising model whichhas the smallest size larger than the size detected from the coefficientinformation.

Further, the CPU 34 may select a circuit indicated by the circuitinformation selected based on the coupling information as the secondcircuit in the first modified example.

Further, in a case where a plurality of circuit informations indicatingcircuits having different coupling coefficient accuracy are included,the circuit information storage device 38 may select, based on theaccuracy of the coupling coefficient described in the couplinginformation, one circuit information indicating a circuit capable ofsearching for the ground state of the Ising model.

For example, the CPU 34 selects circuit information indicating a circuitthat performs calculation with an integer type 16-bit precision in acase where all of the plurality of coupling coefficients described inthe coupling information are represented by integers and are in a rangeof −32768 to 32767. Further, in a case where any one of a plurality ofcoupling coefficients described in the coupling information is a decimalcoupling coefficient, the CPU 34 selects circuit information indicatinga circuit that performs calculation with a floating-point type orfixed-point type precision.

Further, the CPU 34 may cause the display device 42 to display theselected circuit information, the detected size of the Ising model, andthe accuracy of the coupling coefficient. As a result, the CPU 34 cannotify the user of these information.

As such, the information processing system 10 according to the secondmodified example detects the size of the Ising model and the accuracy ofthe coupling coefficient included in the J matrix from the couplinginformation in which the coupling coefficient is described, and selects,based on the detected size and accuracy, appropriate circuit informationamong a plurality of circuit informations to configure a circuit in theFPGA 32. As a result, the information processing system 10 according tothe second modified example can save the user the trouble of specifyingthe circuit information and eliminate the risk of specifying incorrectinformation. Note that a method for detecting the format of the filedcoupling information and the size, and a method for detecting theaccuracy of the coupling coefficient are not limited to the abovemethods, and may be any method.

Third Modified Example

Next, a third modified example will be described. The third modifiedexample is applicable to all of the first to fourth embodiments.

In the third modified example, the circuit information storage device 38stores a plurality of circuit informations for implementing circuitsthat perform the search process by using algorithms different from eachother. In the third modified example, the user inputs other informationexcept for information for specifying the algorithm. For example, theuser inputs the definition information (J matrix and h vector) and thecontrol parameter.

In the third modified example, the CPU 34 selects two or more circuitinformation with different algorithms for calculating the main variable(x_(i)) and the auxiliary variable (p_(i)) in the main variable updateprocess and the auxiliary variable update process among a plurality ofcircuit informations. Then, the CPU 34 sequentially reconfigures theFPGA 32 according to each of the two or more selected circuitinformation, causes the FPGA 32 to perform the search process, andreceives a search result. In this case, the FPGA 32 acquires the searchresult with the same definition information, the same control parameter,the same initial value of the main variable (x_(i)), and the sameinitial values of the plurality of auxiliary variables (p_(i)) for eachof the two or more circuit information. Then, the CPU 34 outputs thesearch result to the user by displaying a pair of information foridentifying the algorithm and the search result on the display device 42for each of the two or more circuit information.

As the Ising machine 12 changes the algorithm, performance indicatorssuch as a convergence speed and resulting solution accuracy may change.The information processing system 10 according to the third modifiedexample can perform the search process by using a plurality ofalgorithms and output a search result for each of the plurality ofalgorithms to notify the user of an algorithm by which an appropriatesearch result can be easily obtained.

Fourth Modified Example

Next, a fourth modified example will be described. The fourth modifiedexample is applicable to all of the first to fourth embodiments.

As illustrated in FIG. 4 , the FPGA 32 (Ising machine 12) alternatelyrepeats the auxiliary variable update process (S115) for updating theauxiliary variable (y_(i)) and the main variable update process (S118)for updating the main variable (x_(i)) a predetermined number of times.In the fourth modified example, the information processing system 10further includes an update history storage device that stores the updatehistory of N main variables (x_(i)) and the update history of Nauxiliary variables (y_(i)) for each repetition in FIG. 4 . For example,the FPGA 32 (Ising machine 12) stores, in the memory, the number ofrepetitions, the values of N main variables (x_(i)), and the values of Nauxiliary variables (y_(i)) in association with one another during theupdate process, and outputs them to the update history storage deviceafter the search process is completed. When an instruction is receivedfrom the user, the CPU 34 (host unit 14) receives the update history ofthe values of N main variables (x_(i)) and the update history of thevalues of N auxiliary variables (y_(i)) stored in the update historystorage device, and causes the display device 42 to display the receivedupdate history in a form of, for example, a graph.

As a result, the information processing system 10 according to thefourth modified example can allow the user to refer to the updatehistory of the values of N main variables (x_(i)) and the update historyof the values of N auxiliary variables (y_(i)) for a study of thecombinatorial optimization problem or the like.

While certain embodiments have been described, these embodiments havebeen presented by way of example only, and are not intended to limit thescope of the inventions. Indeed, the novel embodiments described hereinmay be embodied in a variety of other forms; furthermore, variousomissions, substitutions and changes in the form of the embodimentsdescribed herein may be made without departing from the spirit of theinventions. The accompanying claims and their equivalents are intendedto cover such forms or modifications as would fall within the scope andspirit of the inventions.

1-13. (canceled)
 14. An information processing apparatus, comprising: ahost unit connected to an Ising machine via an interface, the host unitbeing configured to control the Ising machine, wherein: the Isingmachine includes a reconfigurable semiconductor device and is configuredto perform a search process for searching for a ground state of an Isingmodel representing a combinatorial optimization problem, and the hostunit is configured to: prior to the search process, among a plurality ofpieces of circuit information indicating circuits for the semiconductordevice to perform the search process, select one circuit informationindicating a circuit capable of searching for the ground state of theIsing model, and reconfigure the Ising machine according to the selectedcircuit information.
 15. The information processing apparatus accordingto claim 14, wherein, when a search process for searching for a groundstate of a second Ising model is performed in a state where a firstcircuit capable of searching for a ground state of a first Ising modelis configured in the semiconductor device, the host unit is configuredto: determine whether the ground state of the second Ising model issearchable by the first circuit; when searchable, cause the Isingmachine to perform the search process without reconfiguring the Isingmachine; and when not searchable, cause the Ising machine to perform thesearch process by reconfiguring the Ising machine.
 16. The informationprocessing apparatus according to claim 14, wherein: the Ising machinestores N main variables and N auxiliary variables, N being an integer of2 or more, wherein: an i-th main variable of the N main variablescorresponds to an i-th Ising spin of N Ising spins included in the Isingmodel, i being an integer greater than or equal to 1 and less than orequal to N, and an i-th auxiliary variable of the N auxiliary variablescorresponds to the i-th Ising spin; in the search process, the Isingmachine is configured to: alternately repeat an auxiliary variableupdate process for updating the i-th auxiliary variable by the i-th mainvariable and a main variable update process for updating the i-th mainvariable by the i-th auxiliary variable multiple times for the i-thIsing spin, and output, as a search result, a value based on the N mainvariables after alternately repeating the main variable update processand the auxiliary variable update process multiple times; and the hostunit is configured to: prior to the search process, transmit an initialvalue of each of the N auxiliary variables to the Ising machine, andafter the search process, receive the search result from the Isingmachine, and output a solution of the combinatorial optimization problembased on the received search result.
 17. The information processingapparatus according to claim 16, wherein: prior to the search process,the Ising machine sets an initial value of each of the N main variablesto a predetermined value.
 18. The information processing apparatusaccording to claim 16, wherein: prior to the search process, the hostunit transmits an initial value of each of the N main variables to theIsing machine.
 19. The information processing apparatus according toclaim 14, wherein: the Ising machine stores N main variables and Nauxiliary variables, N being an integer of 2 or more, wherein: an i-thmain variable of the N main variables corresponds to an i-th Ising spinof N Ising spins included in the Ising model, i being an integer greaterthan or equal to 1 and less than or equal to N, and an i-th auxiliaryvariable of the N auxiliary variables corresponds to the i-th Isingspin; in the search process, the Ising machine is configured to:alternately repeat an auxiliary variable update process for updating thei-th auxiliary variable by the i-th main variable and a main variableupdate process for updating the i-th main variable by the i-th auxiliaryvariable multiple times for the i-th Ising spin, and output, as a searchresult, a value based on the N main variables after alternatelyrepeating the main variable update process and the auxiliary variableupdate process multiple times; and the host unit is configured to: priorto the search process, transmit an initial value of each of the N mainvariables to the Ising machine, and after the search process, receivethe search result from the Ising machine, and output a solution of thecombinatorial optimization problem based on the received search result.20. The information processing apparatus according to claim 19, wherein:prior to the search process, the Ising machine sets an initial value ofeach of the N auxiliary variables to a predetermined value.
 21. Theinformation processing apparatus according to claim 19, wherein: priorto the search process, the host unit transmits an initial value of eachof the N auxiliary variables to the Ising machine.
 22. The informationprocessing apparatus according to claim 16, wherein: prior to the searchprocess, the host unit transmits, to the Ising machine, definitioninformation for defining the Ising model and a control parameter forcontrolling the search process.
 23. The information processing apparatusaccording to claim 16, further comprising: a first flag storage circuitconfigured to store a first flag indicating whether or not the searchprocess is completed, wherein: the first flag storage circuit updates avalue of the first flag in response to a notification transmitted fromthe Ising machine when the search process is completed, and the hostunit receives the search result from the Ising machine according to thevalue of the first flag.
 24. The information processing apparatusaccording to claim 16, wherein: when a first search process forsearching for a ground state of a first Ising model is performed andthen a second search process for searching for a ground state of asecond Ising model is performed, the host unit performs a first mainprocess for generating information used for performing the first searchprocess; the Ising machine performs the first search process after thefirst main process is performed by the host unit; the host unit performsa second main process for generating information used for performing thesecond search process during a period in which the Ising machine isperforming the first search process; and the Ising machine performs thesecond search process after the second main process is performed by thehost unit.
 25. The information processing apparatus according to claim24, wherein: when the first search process is completed while the secondmain process is being performed, the host unit transmits a new initialvalue of each of the N auxiliary variables and causes the Ising machineto re-perform the first search process according to the new initialvalue of each of the N auxiliary variables, and when plural searchresults of the first search process with different initial values of theN auxiliary variables are received while the second main process isbeing performed, the host unit generates a search result of the firstsearch process based on the received plural search results.
 26. Theinformation processing apparatus according to claim 16, furthercomprising a circuit information storage device configured to store aplurality of pieces of circuit information.
 27. The informationprocessing apparatus according to claim 16, wherein: when performing thesearch process for searching for a ground state of a second Ising modelthat is searchable by a first circuit in a state where the first circuitcapable of searching for a ground state of a first Ising model isconfigured in the semiconductor device, the host unit: compares a firsttime representing an estimated execution time of the search processperformed by the first circuit with a second time including areconfiguration time for reconfiguring the semiconductor device as asecond circuit and an estimated execution time of the search processperformed by the second circuit, and when the second time is shorterthan the first time, reconfigures the semiconductor device as the secondcircuit and causes the Ising machine to perform the search process; andthe second circuit is a circuit which is capable of searching for theground state of the second Ising model and for which a search time isshorter than that of the first circuit.
 28. The information processingapparatus according to claim 16, wherein: the host unit: acquirescoefficient information including a plurality of coupling coefficientsthat define the Ising model; and selects, based on a number of theplurality of coupling coefficients included in the coefficientinformation, one circuit information indicating a circuit capable ofsearching for the ground state of the Ising model among the plurality ofpieces of circuit information.
 29. The information processing apparatusaccording to claim 16, wherein the host unit: acquires coefficientinformation including a coupling coefficient that defines the Isingmodel; and selects, based on an accuracy of the coupling coefficientincluded in the coefficient information, one circuit informationindicating a circuit capable of searching for the ground state of theIsing model among the plurality of pieces of circuit information. 30.The information processing apparatus according to claim 16, wherein:when being instructed to search for the ground state of the Ising model,the host unit: selects two or more pieces of circuit information withdifferent algorithms for calculating the N main variables and the Nauxiliary variables in the main variable update process and theauxiliary variable update process among the plurality of pieces ofcircuit information; for each of the two or more pieces of circuitinformation, sequentially reconfigures the semiconductor device andcauses the semiconductor device to perform the search process, andreceives the search result; and outputs the search result received fromthe semiconductor device.
 31. The information processing apparatusaccording to claim 16, wherein: the Ising machine stores values of the Nmain variables in association with a number of repetitions of the mainvariable update process each time the main variable update process isperformed, and after the search process, the host unit receives thevalues of the N main variables associated with the number of repetitionsof the main variable update process.
 32. An information processingmethod implemented by an information processing apparatus connected toan Ising machine via an interface and configured to control the Isingmachine including a reconfigurable semiconductor device, the Isingmachine being configured to perform a search process for searching for aground state of an Ising model representing a combinatorial optimizationproblem, the method comprising: prior to the search process, among aplurality of pieces of circuit information indicating circuits for thesemiconductor device to perform the search process, by the informationprocessing apparatus, selecting one circuit information indicating acircuit capable of searching for the ground state of the Ising model,and reconfiguring the Ising machine according to the selected circuitinformation.
 33. A computer program product having a non-transitorycomputer readable medium including programmed instructions storedthereon, wherein the instructions, when executed by a computer of aninformation processing apparatus, cause the computer to function as: ahost unit connected to an Ising machine via an interface, the host unitbeing configured to control the Ising machine, wherein: the Isingmachine includes a reconfigurable semiconductor device and is configuredto perform a search process for searching for a ground state of an Isingmodel representing a combinatorial optimization problem, and theinstructions cause the host unit to: prior to the search process, amonga plurality of pieces of circuit information indicating circuits for thesemiconductor device to perform the search process, select one circuitinformation indicating a circuit capable of searching for the groundstate of the Ising model, and reconfigure the Ising machine according tothe selected circuit information.